• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
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    • 专利摘要:
    The present invention relates to data encoding techniques for non-volatile memory storage systems. In a particular embodiment, these techniques can be implemented in the form of a method, consisting for example of writing first data in the memory, reading the first data from the memory, analyzing the first data read from such that the analysis is to determine whether the read data has an error, to encode second data based on the analysis of the first data so that the second data is coded so that it is written to a position adjacent to the error when it is determined that the read data includes the error, and writing the second encoded data in the memory to said position.
    公开号:FR3025928A1
    申请号:FR1558316
    申请日:2015-09-08
    公开日:2016-03-18
    发明作者:Zvonimir Z Bandic；Yongjune Kim；Robert Mateescu；Seung-Hwan Song
    申请人:HGST Netherlands BV；
    IPC主号:
    专利说明:

    [0001] BACKGROUND OF THE INVENTION [0001] Storage systems in non-volatile memory are a type of memory commonly used in computer systems. Nonvolatile memory such as electronic disks and hard disks offer particular advantages such as the ability to store data with high access speeds and data rates. However, a problem associated with a nonvolatile memory (NVM) is the stripping phenomenon which leads to variations of the threshold voltage in programmed cells and to errors. In particular, rapid detachment caused by electrons trapped in tunneling outgoing memory cell charge trapping layers after programming causes errors in memory. This phenomenon and the associated errors are particularly troublesome in a three-dimensional vertical flash memory. Typical methods of remedying desegregation are in part concerned with the engineering of cell structure. However, these conventional techniques generally do not sufficiently compensate for this phenomenon, which leads to an increase in errors. SUMMARY OF THE INVENTION [0002] Data encoding techniques to be written to a nonvolatile storage storage subsystem are described. In one aspect, the present invention relates to a method of encoding data to be written to a memory comprising: writing first data to the memory; read the first data from the memory; analyzing the first data read, in which the analysis consists in determining whether the data read includes an error; encoding second data based on the analysis of the first data, wherein the second data is encoded to be written at a position adjacent the error when it is determined that the read data includes the error; and writing the second data removed in the memory to said position. In some embodiments of the present invention, the memory is a non-volatile memory storage system. In accordance with other aspects of this embodiment, the nonvolatile storage system is an electronic disk. [0005] In accordance with further aspects of this embodiment, the electronic disk is a three-dimensional flash memory. [0006] In accordance with other aspects of this embodiment, the three-dimensional flash memory comprises a plurality of word lines having single-level cells. According to additional aspects of this embodiment, the reading consists in reading the first data from the memory on the basis of a predetermined threshold. According to additional aspects of this embodiment, the predetermined threshold is a read voltage level threshold. According to additional aspects of this embodiment, the analysis consists in comparing the first data read from the memory on the basis of the predetermined threshold with a copy of the first data which is different from the first data stored in the memory. . According to additional aspects of this embodiment, the analysis consists in identifying an error position of a memory cell comprising the error on the basis of the comparison, and in which the position at which the second data must be written is adjacent to the error position of the memory cell. [0011] In accordance with further aspects of this embodiment, the position at which the second data is to be written is in a different word line. According to other aspects of this embodiment, the reading consists in reading the first data from the memory on the basis of a plurality of predetermined thresholds. According to other aspects of this embodiment, the analysis consists in comparing the first data read from the memory on the basis of a first of the plurality of predetermined thresholds to the first data. read from the memory based on a second of the plurality of predetermined thresholds which is different from the first predetermined threshold. [0014] In accordance with further aspects of this embodiment, the analysis involves identifying an error position of a memory cell having the error based on the comparison. According to additional aspects of this embodiment, the three-dimensional flash memory comprises a plurality of word lines having multi-level cells. [0016] In accordance with further aspects of this embodiment, the position at which the second data is to be written is in one of an upper page of a first adjacent line of words different from a line of words containing the first data and a lower page of a second adjacent word line different from the word line containing the first data. [0017] In accordance with other aspects of this embodiment, the encoding is performed by a flash memory controller. In accordance with further aspects of this embodiment, the error is caused by unstacking. [0019] In accordance with further aspects of this embodiment, the second data is written to the memory at said position to cause intercell interference with the first data. Another aspect of the present invention relates to a computer program product consisting of a series of executable instructions on a computer, the computer program product performing a data encoding process to be written to a memory; the computer program embodying the steps of: writing first 25 data into the memory; read the first data from the memory; analyzing the first data read, in which the analysis consists of determining whether the read data comprises an error; encoding second data based on the analysis of the first data, wherein the second data is encoded to be written at a position adjacent the error when it is determined that the read data includes the error; and writing the second coded data in the memory to said position. In some embodiments, the techniques may be implemented in the form of a computer program product consisting of a series of instructions executable on a computer, the computer program product performing a process for controlling power on an Express Peripheral Component Interconnect (PCIe) interface; the computer program embodying the steps of: writing first data to the memory; read the first data from the memory; analyzing the first data read, in which the analysis consists in determining whether the data read includes an error; encoding second data based on the analysis of the first data, wherein the second data is encoded so that it is written to a position adjacent to the error when it is determined that the read data includes the error; and writing the second encoded data in the memory to said position. In some embodiments, these techniques may be implemented in the form of a data encoding system to be written to a memory, the system comprising: a write module that writes first data in the memory ; a read module that reads the first data from the memory; an analysis module that analyzes the first 20 read data, wherein the analysis is to determine whether the read data includes an error when it is determined that the read data includes the error; an encoding module which encodes second data based on the analysis of the first data, wherein the second data is encoded to be written at a position adjacent to the error; and a coded data writing module which writes the second coded data in the memory to said position. The present invention is hereinafter described in more detail with reference to exemplary embodiments thereof which are illustrated in the accompanying drawings. Although the present invention will be described hereinafter with reference to exemplary embodiments, it should be noted that the present invention is not limited thereto. Those skilled in the art having access to the guidelines presented herein will be able to identify additional embodiments, modifications, and embodiments, as well as other areas of use, that fall within the scope of this disclosure. invention as described herein, and in connection with which the present invention may be particularly useful.
    [0002] BRIEF DESCRIPTION OF THE DRAWINGS [0024] In order to facilitate a better understanding of the present invention, reference will now be made to the accompanying drawings, in which like elements are designated by like reference numerals. These drawings are not to be construed as limiting the present invention and are presented by way of example only. Figure 1 shows a block diagram illustrating a computer architecture according to an embodiment of the present invention. Figure 2 shows a block diagram illustrating a computer system according to an embodiment of the present invention. FIG. 3 illustrates an exemplary block diagram illustrating a nonvolatile storage system according to an embodiment of the present invention. Fig. 4 is a block diagram illustrating an encoding control module according to an embodiment of the present invention. FIG. 5 is a flowchart illustrating a data coding method for nonvolatile storage systems according to an embodiment of the present invention. Figures 6A-6B show memory cells according to an embodiment of the present invention. Figures 7A and 7B show memory cell voltage distributions according to an embodiment of the present invention. FIGS. 8A-C show examples of variations in threshold voltage distributions over time caused by writing data into memory cells in accordance with an embodiment of the present invention. FIGS. 9A and 9B show another example of threshold voltage distributions of memory cells according to an embodiment of the present invention. Figures 10A and 10B show an example of memory cell threshold voltage distributions in accordance with an embodiment of the present invention. Figures 11A and 11B show an example of memory cell threshold voltage distributions in accordance with an embodiment of the present invention. Figures 12A and 12B show an example of memory cell threshold voltage distributions in accordance with an embodiment of the present invention. Figs. 13A and 13B show an example of memory cell threshold voltage distributions in accordance with an embodiment of the present invention. [0038] Fig. 14 shows an example of an input / output concept of a memory cell according to an embodiment of the present invention. Fig. 15 shows another example of intercell interference in accordance with an embodiment of the present invention. Figure 16 shows memory cells according to an embodiment of the present invention. Fig. 17 shows an example of memory cell threshold voltage distributions in accordance with an embodiment of the present invention. Fig. 18 shows an example of memory cell threshold voltage distributions in accordance with an embodiment of the present invention. Figure 19 shows an example of memory cell threshold voltage distributions in accordance with an embodiment of the present invention. [0044] Figure 20 shows an example of memory cell threshold voltage distributions in accordance with one embodiment of the present invention. Fig. 21 shows an example of memory cell threshold voltage distributions in accordance with an embodiment of the present invention. Fig. 22 shows an example of memory cell threshold voltage distributions in accordance with an embodiment of the present invention. Description [0047] The present invention generally relates to the encoding of data to be written to a non-volatile memory. According to one aspect of the present invention, the data encoding can take into account the phenomena known as unstacking and intercellular interference (ICI, Inter-Cell Interference). One type of dépiégeage is the rapid dépiegeage caused by electrons trapped in tunneling outgoing memory cell charge trapping layers after programming. Intercellular interference (ICI) is parasitic capacitance coupling between adjacent memory cells having an effect on threshold voltages. In some aspects of the present invention, the memory cells undergoing stripping may be identified and the following data may be written to the memory such that intercellular interference (ICI) is intentionally caused between the memory cells undergoing dépiégeage and the memory cells storing the new data. As a result, errors caused by stripping can be reduced. Figure 1 shows a block diagram illustrating a computer architecture 100 according to an embodiment of the present invention. Computer architecture 100 may include additional elements that are not shown. The computer architecture 100 may contain client computer systems 110, 1,20 and 130, as well as servers 150 and 160. The client computer systems 110, 120 and 130, as well as the servers 150 - 7 - 3025928 and 160 may implement the computer system 200 shown in FIG. 2. Each of the clients 110-130 and the servers 150-160 can be communicatively connected to a network 140. The server 150 can be connected to a plurality of storage devices 152 154. Clients 110-130 may also be connected to a plurality of storage devices (not shown). The server 160 may be connected to a plurality of storage devices 162 to 164. Although only two storage devices connected to the servers 150 and 160 have been illustrated, additional storage devices may be provided. In some cases, the storage devices 152, 154, 162, and 164 may be non-volatile memory storage systems. By way of example, the storage devices 152, 154, 162, and 164 may be a semiconductor memory (for example a flash memory, a NAND flash, etc.), an optical memory, or a magnetic memory . FIG. 2 is a block diagram illustrating a computer system 200 in accordance with an embodiment of the present invention. The computer system 200 may contain a bus 210 connecting subsystems of the computer system 200, among which a central processor 214, a system memory 216 (for example, a RAM (Random Access Memory), a ROM (Read Only Memory, a flash RAM, etc.), an I / O controller 218, and a network interface 220. The network interface 200 can connect the system via communication. computer 200 to a network 222 (e.g., a local area network, a wide area network, the Internet, etc.). The bus 210 may also connect a storage interface 230 in the memory 232, a non-volatile memory interface 234 in a non-volatile memory 236, and a Host Bus Adapter (HBA) to a serial ATA bus. (SATA) 240. The SATA bus 240 can connect the computer system 200 to additional storage systems. The computer system 200 may contain additional devices or sub-systems not shown.
    [0003] FIG. 3 is a block diagram illustrating a non-volatile memory storage system 300 in accordance with an embodiment of the present invention. The non-volatile memory storage system 300 may include a host system 310, a memory controller. 320, and storage systems in non-volatile memory 332-336. The non-volatile memory storage system 300 may be implemented on any of the clients 110-130 and the servers 150 and 160. By way of example, any of the clients 110-130 and servers 150 and 160 may be the host system 320 having at least one CPU (CPU) 312 implementing application software 314. In some cases, the host system 310 may run application software 314 on to least one CPU 312 for performing operations on the non-volatile memory storage systems 332-336 through the memory controller 320. The application software 310 may be any applicable software for perform operations (read, write, erase, control, etc. operations) on the non-volatile memory storage system 300. For example, the application software 310 can read or write stored data s any of the non-volatile memory (NVM) storage systems 332-336. The application software 310 can implement these operations on the NVM storage systems 332-336 via the memory controller 320. The memory controller 320 shown in FIG. memory for performing operations on connected NVM storage systems 332-336. In particular, the memory controller 320 can provide processors (for example, the CPU 312) implementing the application software 314 accessing the NVM storage systems 332-336. In some cases, the memory controller 320 may be implemented on each of the NVM storage systems 332-336 or as part of a separate computer system (e.g., the server 150). In other cases, a single memory controller may be provided to control NVM storage systems 332-336. The controller 320 may provide buffers or queues to temporarily store operations to be implemented on the NVM storage systems 332336. The controller 320 may also encode data to be written to the NVM storage systems. 332-336. Fig. 4 shows a coding control module 400 according to an embodiment of the present invention. As illustrated, the coding control module 400 may contain one or more components, among which a fault detection module 410, t / n coder module 420, and a control module 430. - 9 - 3025928 [0054] The module The fault detection system 410 can detect faults within an NVM storage system. For example, the fault detection module 410 can detect defects within an NVM storage system such as the NVM storage systems 332-336. In some embodiments, the fault detection module 410 can detect faults in an NVM storage system by reading data from the NVM storage system after writing data to the NVM storage system. In some cases, data can be replayed from the NVM immediately after writing. This fault information can then be supplied to the encoder module 420 to compensate for any defects or errors in writing new data in the NVM storage system. In some embodiments, the sensing module 410 may determine defects caused by stripping in the NVM storage system. De-scavenging is caused by electrons trapped in tunneling charge trapping layers after programming of the memory cell. As a result of the unstacking, charges are lost and the threshold voltage of the corresponding memory cells degrades the threshold voltage distribution. This is described and shown in more detail below. De-stacking generally occurs immediately after a write operation has been performed and reaches saturation in less than about one second. In order to determine defects caused by unstacking, the fault detection module 410 can read data from the NVM after writing the data using a predetermined voltage threshold (VT) and compare the data read with the information that has been read. previously written. Alternatively, the module 410 can read the data based on multiple voltage thresholds and compare the results. Based on this comparison, the memory cells undergoing deskewing and the locations corresponding thereto (for example, a word line, a bit line, and a string selection line) can be identified. The encoder module 420 may encode data to be written to an NVM storage system based on a predetermined algorithm. In some cases, the encoder module 420 may receive fault information from the fault detection module 410 and integrate this information when coding the data to be written to the NVM storage system. For example, the encoder module 420 may code and map the cell locations of the data to be written to the NVM to account for the memory cells undergoing garbage collection. In some embodiments, the encoder module 420 may also consider intercell interference when encoding the data to be written. For example, the encoder module 420 may encode the data to be written in such a way that it is intentionally stored at a memory location near the memory cell undergoing deskew in order to intentionally induce intercell interference. . As a result of encoding and writing the data at the near location of the memory cell undergoing debonding, a charge may be injected into the memory cell undergoing stripping leading to an increase in its threshold voltage caused by intercellular interference. The encoder module 420 may provide the coded data to the control module 430 for later writing coded data in the NVM such that when the data is written to the memory, the errors due to the deskew can be reduced. The control module 430 may cause data to be written to and read from an NVM storage system while performing additional background task operations. In some embodiments, the control module 430 may receive encoded data from the encoder module 420 and cause the data to be written to an NVM storage system (eg NVM storage systems 332-336). The control module 430 may also cause the data to be read from an NVM storage system (e.g. NVM storage systems 332-336). By way of example, the control module 430 can read data from the NVM after writing data and provide this read data to the fault detection module 410 for fault detection purposes. FIG. 5 represents a method 500 of data encoding according to an embodiment of the present invention. In some embodiments, method 500 may be implemented at a hardware level, such as controller 320. At block 510, method 500 may begin. In block 512, data can be written to the memory. In some embodiments, the control module 430 may cause the data to be written to the memory. The data written in the memory at block 512 may be user data-3025928 or a predetermined data sequence. In some cases, the memory may be an NVM storage system such as a NAND flash memory. An example of writing data into the memory is described below with reference to Fig. 7. After the data has been written to block 512, the entire process can proceed to block 514. [0060f At block 514 , the data written in block 512 can be read from the memory. In some embodiments, the control module 430 may cause the previously written data in block 512 to be read from the memory (for example a flash memory). In some cases, the control module 430 can read the data from the memory multiple times based on different threshold values (VT). The data read from the memory 10 can then be provided to the fault detection module 410 for analysis. After the data has been read from the memory at block 514, the entire process may proceed to block 516. At block 516, data read from the memory at block 514 may be analyzed to determine if errors have occurred. are present in the data and also if corresponding defects are present in memory cells storing the data. In some embodiments, the fault detection module 410 may analyze the read data to identify memory cells undergoing garbage collection. For example, the fault detection module 410 can store the original data written at block 512 and compare the read data from the memory at block 514 to identify defective memory cells. The locations of memory cells undergoing debonding may also be determined based on the comparison. In another example, the fault detection module 410 may use the data read from the memory on the basis of different voltage thresholds to identify errors and memory cells undergoing debugging. An example of this is described below with reference to Fig. 8. After the data has been analyzed at block 516, the entire process can proceed to block 518. In block 518, new data needs to be available. written in the memory can be encoded. In some embodiments, the data may be encoded by the encoder module 420. The data to be written may be encoded using the fault information determined at block 516. In particular, the encoder module 420 may determine the locations. 3025928 of memory cells (eg a word line, a bit line, and a string selection line) and use this information when writing new data. By way of example, data to be written may be encoded in such a way that the unwinding effect in a memory cell on the i-th word line (WL, Word Line) can be controlled by intercell interference. intentional (ICI) parasitic capacitance coupling between adjacent cells-due to the (i + 1) -th line of words. As a result, the intentional ICI can compensate for a decrease in the threshold value of a memory cell in the i-th line of words since the intentional ICI can increase the threshold voltage in a cell causing the interference. . Examples of data encoding are described in detail below.
    [0004] After the new data has been coded in block 518, the entire process can proceed to block 520. In block 520, the encoded data may be written to the memory. In some embodiments, the data may be written to the memory (eg flash memory) by the control module 430. After the data has been written to block 520, the entire process may proceed to block 522 At block 522, the process can be terminated. In some embodiments, the process may return to step 510 and may be repeated periodically or continuously. Figures 6A-6B show memory cells according to an embodiment of the present invention. The memory cells shown in FIGS. 6A-6B may correspond to the memory storing the data described above with reference to FIG. 5. In particular, FIGS. 6A-6B represent memory cells located in a segment of FIG. a 3D vertical flash memory array architecture according to an embodiment of the present invention. FIG. 6A shows a network of 3D vertical flash memories 610 having multiple word line planes, including the word lines: W1 (, + 1) 612, WL (,) 614, and WL (, _ 1) 616, and multiple lines of bits connecting the word lines: BLo_i) 618, 1340620, and BL04- /) 622. The memory cells are also arranged in groups of lines of selection of strings (SSL, String Selection Line ): SSL (k_i) 624, SSL (k) 626, and SSL (k +)) 628. Words lines 3025928 and additional bit lines may be present although they are not illustrated. Fig. 6A further illustrates a case of intercell interference 630 between a memory cell contained in the word line 612 and the word line 614. Fig. 6B illustrates a cross section 650 of a word line plane having multiple lines of words. By way of example, FIG. 6B may for example correspond to a cross-section of the 3D vertical flash memory array 610, including W4 + 1) 612. Plan 650 has multiple word lines 652, 654, and 656 each having multiple memory cells (e.g., 658). In some embodiments, the memory cells (e.g., 658) may have a nitride layer within an oxide-nitride-oxide (ONO) stack grown in the form of a charge trapping layer along the circumference of the thin vertical polysilicon channel and surrounded by metal grids along the WL plane. The threshold voltage of a memory cell may correspond to the logic value (for example 0 or 1) stored in a memory cell. In one example, V (i, j, k) may correspond to the threshold voltage of the memory cell (i, j, k). The memory cell (i, j, k) may correspond to the memory cell of the 3D vertical flash memory array 610 shown in FIG. 6A, located at the i-th line of words, at the j-th BL, and the k-th group of lines of selection of chains (SSL). Intercellular interference (ICI) may occur relative to adjacent memory cells due to parasitic capacitance coupling between adjacent cells. The shift of the threshold voltage AmV (i, j, k) of the cell (i, j, k) due to intercellular interference (ICI) can be calculated on the basis of the following formula: AloV (if, k) = yWL-to-WL (AV (i-li, k) + AV (i + 1 j, k) + yBL-to-BL (AV (i, j-1, k) + AV (if + 1 , k) (1) + 7SSL-to-SSL AV (ij, k-1) + AV (i, j, k + 1) AV (± 1 ± 1, k + 1) represents the offsets of the voltage of threshold of adjacent cells after the cell (if, k) has been written yWL-to-WL is the coupling ratio between a WL plane and an adjacent WL plane yBL-to-BL corresponds The coupling ratio is a bit line (BL) and an adjacent BL, and ySSL-to-SSL is the coupling ratio between an SSL group and the adjacent SSL group. Intercellular interference (ICI) between adjacent WL planes in a 3D vertical flash memory is reduced compared to conventional 2D flat flash memory since the charge trapping layer in the 3D vertical flash memory is much thinner than the floating gate layer contained in the 2D flash memory. However, intercellular interference (ICI) between adjacent WL planes increases as the physical distance between WL planes is reduced when the cell density is higher. As a result, by setting y = yWL-to-WL and yBL-to-BL = ySSL-to-SSL = 0, the intercellular interference model (ICI) of relation (1) can be simplified to: AicIV (if , k) = y (AV (i-1j, k) + AV (i + 1 I, k)). (2) This model of intercellular interference (ICI) between adjacent memory cells in a 3D vertical flash memory can be exploited when encoding new data to be written into the memory in order to reduce the errors caused by unstacking. Figures 7A and 7B show memory cell voltage distributions according to an embodiment of the present invention. The voltage distributions of the memory cells shown in Figs. 7A and 7B may correspond to the data write to block 512 of Fig. 5. In particular, Fig. 7A represents a single single-level cell (SLC, Single -Level Cell) for storing B bits per cell, where B = 1 and corresponding distributions of the threshold voltage. The x-axis corresponds to the threshold voltage (VT) of the memory cells and the y-axis corresponds to the number of memory cells having this threshold voltage. Initially, the memory cells may be erased or deprogrammed so that their threshold voltage distribution is in a lowest state, So 710. When writing data to the memory cells, the threshold voltages of the The cells are augmented according to one of a plurality of methods used for write operations (eg, an Incremental Step Pulse Programming (ISPP) method) such that The memory cells enter a programmed state 712. In this programmed state 712, the memory cells have a higher voltage distribution. Figure 7B shows an example of a multi-level cell (MLC) for storing B bits per cell, where B = 2. In other cases, multi-level (MLC) stores B bits per cell, where B> 2. Figure 7B shows the memory cells of the multi-level cell memory (MLC) initially in an erased state such that their threshold voltage is at the lowest state So 714. During writing of data in the memory cells, the threshold voltages of the memory cells are increased so that the cells are in a first programmed state 716, a second programmed state 718, and a third programmed state 720. These different programmed states can correspond to different logical values (for example, 00, 01, 10, 11). [0071] Figs. 8A-C show examples of variations in threshold voltage distributions over time caused by writing data into memory cells in accordance with an embodiment of the present invention. The voltage distributions of the memory cells shown in FIGS. 8A-C can correspond to the writing of data to block 512, to reading the data written at block 514, and to the analysis of the data read at block 516 of FIG. Figure 5. By measuring the distribution of the threshold voltages of the programmed memory cells after programming and comparing the results, it is possible to identify the memory cells undergoing desegregation. As illustrated in FIG. 8A, a memory cell contained in the word line i can be initialized in a first state So 810 before writing data and programmed to a second state Si 812 after the writing of the data. data. In this case, the first state So may correspond to a binary "1" while the second state may correspond to a binary "0". However, in other methods, the first state S0 may correspond to a "0" binary while the second state may correspond to a "1" binary. FIG. 8A further illustrates the programming of the memory cells before unwinding occurs so that the second state Si 812 exceeds the read level threshold voltage T 1 and the check level threshold voltage y . The read level threshold voltage ri may correspond to the voltage level used when reading the data from the memory cell although the check level threshold voltage can be used during the programming of the memory cells to the voltage values specific to the read level ri and the check level y may differ according to the particular memory concept. FIG. 8B illustrates a case of the threshold voltage distribution of memory cells contained in the line of words i after the unstacking, in particular due to the dépiegeage. rapiçie.
    [0005] As illustrated in FIG. 8B, the distribution of the threshold voltage levels 814 in the memory cells on the word line i after programming can be degraded so that the number of memory cells having the appropriate voltage decreases by because of rapid deskewing. Not all memory cells experience the same degree of unwinding, and the degree of unwinding can vary over time. In order to detect the memory cells that are experiencing rapid desegregation, the written data can be read after a predetermined time has elapsed since writing to allow the completion of any unwinding. FIG. 8C illustrates a case of reading the data by using the reading level threshold voltage r 1 and reading the data separately using an identification level threshold voltage.. On the basis of a comparison of the two readings, it is possible to identify the memory cells on the word line i undergoing rapid deskew 816. By way of example, if the threshold voltage of a cell is between and,, this cell can be identified as undergoing rapid deskew and the encoder module 410 can obtain the location of that cell. In some cases, the identification voltage level peut may correspond to the verification level threshold voltage y. As noted above, the degree of dépiegeage for each memory cell may be different and vary over time. As a result, the identification voltage level peut can be changed by taking into account the frequency at which the detacking is detected. For example, the identification voltage level peut can be changed upon detection of a predetermined number of memory cells undergoing rapid deskew. FIGS. 9A and 9B show another example of memory cell threshold voltage distributions in accordance with an embodiment of the present invention. The voltage distributions of the memory cells shown in Figs. 9A and 9B may correspond to the memory cells in an initialized or erased state before writing data to block 512 of Fig. 5. Fig. 9A illustrates a first word line i 910 comprising memory cells C (,, 1.1) 912, Co, j) 914, and C (,, j + i) 916. The first word line i 910 can correspond to the line of words described above and shown in Figure 6A.
    [0006] FIG. 9A further illustrates a threshold voltage distribution 918 of the memory cells contained in the first word line i 910. FIG. 9B illustrates a second word line i-1 950 comprising memory cells C (i 952, C (t_i, j) 954, and C (, i, ji.i) 956 being in a first state. In this first state, the memory cells of the word line i-1 have a threshold voltage distribution 958. [0076] FIGS. 10A and 10B show an example of memory cell threshold voltage distributions in accordance with FIG. an embodiment of the present invention. In particular, Figs. 10A and 10B show an example of threshold voltage distributions corresponding to the write performed in the i-1 950 word line shown in Fig. 9B. This may correspond to the writing of the data to block 512 of FIG. 5. FIG. 10A shows a first word line i 1010 comprising memory cells Co, j_1) 1012, C (Z, j) 1014, and Co 10A). FIG. 10A further illustrates a threshold voltage distribution 1018 of the memory cells contained in the first word line i 1010. This voltage distribution may correspond to the voltage distribution 918 shown in FIG. 9A since the word line i 1010 is in the same first state. Figure 10B illustrates an example of writing data in a second word line i-1 1050. Figure 10B shows the second word line i-1 1050 including memory cells C (; 1052, C (, i, j) 1054, and C (, _], j + 1) 1056. The word line i-1 1050 of FIG. 10B may correspond to the word line i-1 950 shown in Figure 9B. As illustrated in FIG. 10B, the word line i-1 goes from a first threshold voltage distribution 1058 to a second threshold voltage distribution 1060 due to the charge injection into the memory cells C (FIG. 1052, 44, j) 1054, and C (, i, j + 1) 1056. Fig. 10B illustrates the voltage distribution 1060 immediately after the writing of the data and before rapid destacking occurs. Figures 11A and 11B show an example of memory cell threshold voltage distributions in accordance with an embodiment of the present invention. In particular, Figs. 11A and 11B show an example of threshold voltage distributions immediately after writing in the i-1 word line 1050 shown in Fig. 10B. This may correspond to the writing of the data to block 512 of FIG. 5. FIG. 11A represents a first word line 1110 comprising memory cells C (1) 1112, C (11), 1114, and C (,, j + 1) 1116. Fig. 11A further illustrates a threshold voltage distribution 1118 of the memory cells contained in the first word line i 1110. This voltage distribution may correspond to the voltage distribution 918. shown in Fig. 9A and voltage distribution 1018 shown in Fig. 10A. FIG. 11B illustrates an example of rapid dépiégeage occurring on a second line of words i-1 1150. FIG 10B represents the second line of words i-1 1150 comprising memory cells C (, _ 1, j_1) 1152, C (, i, J) 1154, and C (, _ /, j + i) 1156. The word line i-1 1150 of FIG. 10B may correspond to the word line i- / 950 shown in FIG. FIG. 9B and line 15 of i-1 words 1050 shown in FIG. 10B. As illustrated in FIG. 11B, the voltage distribution 1160 of the memory cells on the word line 1150 is shifted due to rapid deskew. The rapid deskew is caused by electrons tunneling out of the memory cells such that the voltage distribution of the memory cells is changed. Figures 12A and 12B show an example of memory cell threshold voltage distributions in accordance with one embodiment of the present invention. In particular, Figs. 12A and 12B show an example of threshold voltage distributions during the reading of the word line i-1 1250. The word line i-1 1250 may correspond to the word line i- / 1150 shown in Figure 11B. The reading of the word line i-1 1250 may also correspond to the reading of data at block 514 and the analysis of the data at block 516 of FIG. 5. FIG. 12A represents a first word line i 1210 comprising memory cells C (i, pi) 1212, C (,, j) 1214, and C (i + i) 1216. FIG. 12A further illustrates a threshold voltage distribution 1218 of the memory cells contained in the first line of words 1210. This voltage distribution may correspond to the voltage distribution 1118 shown in FIG. 11A. FIG. 12B illustrates an example of reading data previously written in memory cells 4_1, j_1) 1252, 44, j) 1254, and C (; _ 1, j + 1) 1256 on the word line i- / 1250 to determine if rapid deskew has occurred. In some cases, the data from the i-1250 word line can be read using a threshold voltage 1214. This data read can then be compared to a stored copy of the data to identify possible errors. In this case, it can be determined that the cell 4_1, j) 1254 undergoes rapid dépiegeage since the voltage distribution at the location of this cell has fallen below the threshold voltage 1214. for example, the controller 320 can store a copy of the data and compare it to the read data. In another case, the data from the i-1250 word line can be read using a read threshold voltage (not shown) and another threshold voltage 1214 corresponding to a verify voltage. On the basis of a comparison of the two readings using the different threshold voltages, it can be determined that the cell j) 1254 is undergoing stripping since its voltage distribution is below the threshold voltage 1214 but above reading threshold voltage (not shown). Figs. 13A and 13B show an example of memory cell threshold voltage distributions in accordance with an embodiment of the present invention. In particular, FIGS. 13A and 13B show an example of threshold voltage distributions during the writing done in the word line i 1310. In particular, FIGS. 13A and 13B show an example of coding and writing of data. corresponding to blocks 518 and 520 of Fig. 5. Fig. 13A illustrates the word line i 1310 comprising memory cells C (1), 1312, C (13), 1314, and C (i, j). + i) 1316. The word line i 1310 corresponds to word line i 1210 of FIG. 12A. FIG. 13B shows the word line 1350 comprising cells C (, _], j_1) 1352, C (, _ /, f) 1354, and C (, _ 1, j + 1) 1356. The line of words i-1 1350 corresponds to line of words i- / 1250 of FIG. 12B. In this case, the cell C (i4, j) 1354 undergoes rapid dépiegeage. As a result, data may be encoded (e.g., mapped) in memory cell 4, j) 1314 of word line i 1310 which is adjacent to cell j) 1354 contained in word line i-1 - 20- 3025928 1350 to cause an intentional ICI. FIG. 13B illustrates a write made in the word line i 1310, in particular the memory cell C (,, j) 1314, so that the threshold voltage distribution can go from a first state 1318 to a second state 1320. As a result, a charge can be injected into the cell C (,, i, j) because of the intentional ICI so that the voltage distribution can pass from a degraded distribution to a distribution. 1362 which corresponds more exactly to the desired programming state. Fig. 14 shows an example of an input / output concept of a memory cell according to an embodiment of the present invention. Usually, a binary memory cell may be considered defective if its cell value is set to a particular value (0 or 1) regardless of the channel input. This is illustrated in 1410 in Fig. 14 which represents an input at 0 and 1 providing an output at 1. On the basis of this concept, the cell C (1, f) adjacent to the cell C (, _ i, j) undergoing depigmenting may be considered frozen in accordance with the coding system of the present invention. For example, if the coding method requires that the voltages exceeding the threshold correspond to "0", then the cell C (11) can be considered as set to "0". Therefore, when coding new data in the memory, C (,, j) can be coded as a "0" so that when the data is written, a voltage is injected into the cell and that ICI increases the threshold voltage of the cell (i-1, j) undergoing stripping. FIG. 15 illustrates another example of an intercell interference 20 according to an embodiment of the present invention. In this example, FIG. 13 illustrates the line of 1 + 1 words 1510 comprising memory cells C (, + /, .1_1) 1512, co + ,,,) 1514, and C (, + /, j + i). 1516. Fig. 15 further comprises a word line 1550 comprising memory cells C (,, j_i) 1552, C (,, j) 1554, and C (i, j + i) 156. In this case, the Cm cell 1552 on the word line i 1550 has been identified as being rapidly detuned by reading the word line as described above. On the basis of the identification of the Co j) 1512 cell being unstacked, data can be encoded and written in C (, + 4) 1515 so that the threshold voltage of the cell g, j) can increase. because of the intentional ICI. Figure 16 shows memory cells according to an embodiment of the present invention. In particular, Fig. 16 shows a plurality of word lines of a multi-level cell memory (MLC). The multi-level memory cell is capable of storing multiple bits (eg, two) per cell. An MLC memory can be written in lower and upper pages in an architecture entirely based on bit lines (ALB, All-Bit-Line) in such a way that all the 5-bit lines of a line words are programmed simultaneously. This method is illustrated in Figure 16 which shows an example of writing in memory in the following order: 1) page 0 in the lower page of the word line 0; 2) page 1 in the lower page of the word line 1; 3) page 2 in the upper page of the word line 1; 4) page 3 in the lower page of the word line 2; 5) page 4 in the upper page of the word line 1, etc. In accordance with embodiments of the present invention, the intentional ICI may be implemented in accordance with this method when pages in adjacent word lines are written. Fig. 17 shows an example of memory cell threshold voltage distributions in accordance with an embodiment of the present invention. In particular, Fig. 17 illustrates threshold voltage distributions of memory cells based on data contained in a MLC memory according to the method described above. As illustrated in Fig. 17, a word line having a lower page (lower page) and a higher page (upper page) may initially be in a first state 1710 in which its voltage distribution 1712 is in an erased state. The word line may switch to a second state 1720 in which the lower page is programmed and provides a voltage distribution 1722 corresponding to a logic value 10. After writing the lower page, the word line may be changed to a second one. third state 1730 in which the top page (top page) is programmed and provides a voltage distribution 1732 corresponding to a logical value of 1001 in the high page and 1100 in the low page. Fig. 18 shows an example of memory cell threshold voltage distributions in accordance with an embodiment of the present invention. In particular, FIG. 18 illustrates the possibilities of implementing an intentional ICI in order to correct depleted cells on the low page (i) of the word line. Figure 18 illustrates multiple word lines: WLO 1810, WL1 1820, WL2 1830, and WL3 1840, each word line having a lower page (lower page) and a higher page (upper page). In this case, data was written in the two pages of WLO 1810, the lower page of WL1 1820, and the lower page (i) of WL2 1830. By rereading the data from the lower page (i) of WL2, it It can be determined that cells on the bottom page (i) are undergoing peeling. This may correspond to the step of reading the data and analyzing the data at blocks 514 and 516 of FIG. 5. In particular, reading the data from the lower page (i) of WL2 1830 may indicate that a part of the voltage distribution 1812 is below the threshold voltage 1850. When writing the following data in the low page on WL3 1840 and the high page on WL1 1820, an intentional ICI can be introduced in order to compensate for the unwinding. Fig. 19 shows an example of memory cell threshold voltage distributions in accordance with an embodiment of the present invention. Fig. 19 shows word lines: WLO 1910, WL1 1920, WL2 1930, and WL3 1940 corresponding to the word lines of Fig. 18. As described above with reference to Fig. 18, it was determined that the page lower (i) of WL2 1820 underwent destacking. Fig. 19 therefore represents a first possibility for the intentional ICI by programming the upper page (i + 1) on WL1 1920 to compensate for the unwrapping of the lower page (i) of WL2 1930. However, in order to avoid causing undesirable errors, the voltage distribution (i-2) 1950 can be taken into account. By way of example, the voltage distribution of the lower page (i-2) of WL1 1920 can be taken into account when writing in the upper page (1 + 1) on WL1 1920 so that if (i-2) has a value of "1", then a cell value of "0" can be programmed while if (i-2) has a value of "0", then a cell value of "1" "can be programmed. Accordingly, writing the upper page (i + 1) to WL1 may increase the voltage of the lower page (i) to WL2 1920, resulting in a voltage distribution 1960. [0090] Fig. 20 shows an example memory cell threshold voltage distributions in accordance with an embodiment of the present invention. FIG. 20 represents word lines: WLO 2010, WL1 2020, WL2 2030, and WL3 2040 corresponding to the word lines of FIGS. 18 and 19. In this case, FIG. 20 represents a second possibility of performing an intentional ICI by programming the lower page (i + 2) on WL3 to compensate for the untangling of the lower page (i) of WL2. Data to be written may be encoded - so that the lower page (1 + 2) on WL3 is programmed to a higher voltage distribution (eg, "0"). As a result, the threshold voltage distribution 2050 of the lower page (i) of WL2 can be increased. [0091] Fig. 21 shows an example of memory cell threshold voltage distributions in accordance with an embodiment of the present invention. Fig. 21 shows word lines: WLO 2110, WL1 2120, WL2 2130, and WL3 2140 corresponding to the word lines of Figs. 18-20. In this case, Fig. 21 shows an offset if a voltage distribution of the memory cells on the upper page (1 + 3) of WL2 2130 results from the occurrence of rapid deskew. As a result, the top page (i + 3) contains errors. Fig. 22 shows an example of memory cell threshold voltage distributions in accordance with an embodiment of the present invention. Fig. 22 shows word lines: WLO 2210, WL1 2220, WL2 2230, and WL3 2240 corresponding to the word lines of Figs. 18-21. Fig. 22 shows the implementation of the intentional ICI in writing data in the upper page (i + 5) of WL3 in order to compensate for the debugging occurring in the upper page (1 + 3) of WL2, as described above with reference to Fig. 21. Data to be written in an empty page (i + 5) of WL3 can be encoded taking into account the values written in the lower page (i + 2) of WL3 of such so that if the lower page (1 + 2) has a value of "1", a value of "0" is coded or if, if the lower page (i + 2) has a value of "0", a value of "1" is coded. As a result, the threshold voltages of the upper (1 + 3) page of WL2 can be increased due to the intentionally coded ICI in the upper page (i + 5) of WL3. Other embodiments fall within the scope and the concept of the invention. By way of example, the functionality described above can be implemented by means of software, hardware, firmware, hard cabling, or combinations of any which of these. One or more computer processors operating in accordance with instructions may implement the functions associated with data encoding for NVM storage systems in accordance with the present invention as described above. If this is the case, it is within the scope of the present invention to be able to store such instructions on one or more processor-readable non-transient storage media (e.g., a magnetic disk or other media). storage). In addition, modules implementing certain functions can also be physically located at various positions, for example by being distributed in such a way that parts of certain functions are implemented at different physical locations.
    [0007] The present invention should not be construed as being limited in scope by the specific embodiments described herein. Indeed, various other embodiments and variations of the present invention, in addition to those described herein, will become apparent to those skilled in the art from reading the description presented above and the accompanying drawings. Therefore, these other embodiments and modifications should be considered within the scope of the present invention. On the other hand, although the present invention has been described herein in the context of a particular embodiment in a particular environment for a particular application, those skilled in the art will appreciate that its utility is not limited to them and that the present invention can be advantageously implemented in any number of environments for any number of applications. Accordingly, the claims presented hereinafter should be regarded as covering the entire scope and concept of the present invention as described herein. - 25 -
    权利要求:
    Claims (20)
    [0001]
    REVENDICATIONS1. A method of encoding data to write to a memory comprising: writing first data to the memory; read the first data from memory; analyzing the first read data, the analysis of determining whether the read data includes an error; encoding second data based on the analysis of the first data, the second data being encoded to be written at a position adjacent the error when it is determined that the read data includes the error; and writing the second coded data in the memory to the position.
    [0002]
    2. The method of claim 1, wherein the memory is a storage system in non-volatile memory.
    [0003]
    The method of claim 2, wherein the non-volatile memory storage system is an electronic disk.
    [0004]
    4. The method of claim 3, wherein the electronic disk is a three-dimensional flash memory.
    [0005]
    The method of claim 4, wherein the three-dimensional flash memory comprises a plurality of word lines having single-level cells.
    [0006]
    The method of claim 1, wherein the reading comprises reading the first data from the memory based on a predetermined threshold.
    [0007]
    The method of claim 6, wherein the predetermined threshold is a read voltage level threshold.
    [0008]
    The method of claim 7, wherein the analyzing comprises comparing the first data read from the memory on the basis of the predetermined threshold to a copy of the first data which is different from the first data stored in the memory.
    [0009]
    The method of claim 8, wherein the analyzing comprises identifying an error position of a memory cell having the error based on the comparison, and wherein the position at which the second data is to being written is adjacent to the error position of the memory cell.
    [0010]
    The method of claim 9, wherein the position at which the second data is to be written is in a different word line.
    [0011]
    The method of claim 1, wherein the reading comprises reading the first data from the memory based on a plurality of predetermined thresholds. 15
    [0012]
    The method of claim 11, wherein the analyzing comprises comparing the first data read from the memory based on a first of the plurality of predetermined thresholds to the first data read from the memory based on a second one. of the plurality of predetermined thresholds which is different from the first predetermined threshold. 20
    [0013]
    The method of claim 12, wherein the analyzing comprises identifying an error position of a memory cell having the error based on the comparison.
    [0014]
    The method of claim 4, wherein the three-dimensional flash memory comprises a plurality of word lines having multi-level cells. 25
    [0015]
    The method of claim 14, wherein the position at which the second data is to be written is in one of an upper page of a first adjacent word line different from a word line containing the first data. and a lower page of a second adjacent word line different from the word line containing the first 30 data. -27- 3025928
    [0016]
    The method of claim 1, wherein the encoding is performed by a flash memory controller.
    [0017]
    The method of claim 1, wherein the error is caused by unstacking. 5
    [0018]
    The method of claim 1, wherein the second data is written to the memory at the position to cause intercellular interference with the first data. 10
    [0019]
    A computer program product consisting of a series of executable instructions on a computer, wherein the computer program product performs a data encoding process for writing to a memory; the computer program implementing the steps of: writing first data in the memory; 15 read the first data from the memory; analyzing the first read data, the analysis of determining whether the read data includes an error; encoding second data based on the analysis of the first data, the second data being encoded to be written at a position adjacent to the error when it is determined that the read data includes the error; and writing the second coded data in the memory to the position.
    [0020]
    20. A data encoding system for writing to a memory, the system comprising: a write module that writes first data to the memory; a read module that reads the first data from the memory; an analysis module that analyzes the first read data, wherein the analysis is to determine whether the read data includes an error when it is determined that the read data includes the error; An encoding module which encodes second data based on the analysis of the first data, wherein the second data is encoded to be written at a position adjacent to the error; and a coded data writing module which writes the second coded data in the memory to the position. - 29 -
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    同族专利:
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    US20160077912A1|2016-03-17|
    GB2530175A|2016-03-16|
    DE102015011991A1|2016-04-07|
    GB2530175B|2019-03-13|
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    优先权:
    申请号 | 申请日 | 专利标题
    US201462050415P| true| 2014-09-15|2014-09-15|
    US14/627,580|US9830219B2|2014-09-15|2015-02-20|Encoding scheme for 3D vertical flash memory|
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